1. Field of the Invention
The present invention relates to a method and device for driving a plasma display.
Recently, in display devices, there has been activity in increasing the screen size up the display density and improvements in the capability of displaying a variety of information and the flexibility of placement conditions. Examples of such display devices are a plasma display panel (PDP), a cathode-ray tube (CRT), a liquid crystal display (LCD), an electro-luminescence (EL), a fluorescent display tube and a light-emitting diode. The key factor in the above activity in the development of display devices is to increase the display quality.
Particularly, there has been considerable activity in the development of the plasma display panel because it has various advantages such as no flicker noise, easy implementation of a large-size screen, high luminance and long lifetime. The plasma display panel is categorized in a dual-electrode type and a triple-electrode type. The dual-electrode type realizes a selective discharge (address discharge) and a sustain discharge by means of two electrodes. The triple-electrode type realizes the address discharge by using the third electrode. A color plasma display panel capable of realizing gradation display has a mechanism such that a fluorescent substance formed in a discharge cell is excited by a ultraviolet ray created by the discharge. However, there is a disadvantage in that the fluorescent substrate is susceptible to impact of ions of positive charges simultaneously generated by the discharge. The dual-electrode type has an arrangement in which the fluorescent substance is directly hit by the ions, and the lifetime thereof may thus be shortened.
The triple-electrode type utilizing a surface discharge can realize the color plasma display panel in which the above disadvantage is avoided. The triple-electrode type is categorized in a first arrangement and a second arrangement. In the first arrangement, the third electrodes is formed on a substrate on which the first and second electrodes for the sustain discharge are arranged. In the second arrangement, the third electrode is formed on another substrate opposite the substrate on which the first and second electrodes are arranged. The first arrangement is categorized in two types. The first type has the third electrode arranged above the two electrodes for the sustain discharge. The second type has the third electrode arranged under the two electrodes. There are also a transparent type and a reflection type. In the transparent type, visible light emitted from the fluorescent substance is viewed through the fluorescent substance. In the reflection type, visible light is viewed after it is reflected by the fluorescent substance. The cells in which a discharge takes place are spatially isolated from adjacent cells by means of a rib or barrier. The barrier is provided in a first or second arrangement. In the first arrangement, the barrier is provided on the four sides of each discharge cell and completely seals the discharge cell. In the second arrangement, the barrier is arranged only in one direction, spatial couplings in the other directions are implemented by an appropriate distance between the electrodes, in other words, an appropriate gap therebetween.
The present invention is concerned with the plasma display panels.
2. Description of the Related Art
The present specification is exemplarily directed to a plasma display panel having the following arrangement. The first and second electrodes for the sustain electrode are formed on a first substrate, and the third electrode is formed on a second subatrate opposite the first substrate. The barrier is formed only in the vertical direction, which is orthogonal to the first and second electrodes and is parallel to the third electrode. The sustain electrodes partially have a transparent electrode.
FIG. 1 is a schematic plan view of a plasma display panel having the above arrangement (which can be called a triple-electrode surface-discharge AC type plasma display panel). FIG. 2 schematically shows a vertical section of the plasma display panel, and FIG. 3 schematically shows a horizontal section thereof. FIGS. 2 and 3 show only one discharge cell.
The plasma display panel is generally formed of two glass plates. A front glass plate 18 is equipped with X electrodes 13 and Y electrodes 14, which function as sustain electrodes 19 extending in parallel. Each of the X electrodes 13 and the Y electrodes 14 is made up of a transparent electrode 19a and a bus electrode 19b. The transparent electrode 19a has a role of allowing reflected light coming from a fluorescent substance 17 to pass therethrough. In this regard, the transparent electrode 19a is formed of ITO (which a transparent conductive film having a main component of indium oxide). The bus electrode 19b is required to have a relatively low resistance in order to prevent occurrence of a voltage drop, and is thus made of, for example, Cr or Cu. The sustain electrodes 19 are covered by a dielectric layer (glass layer) 20. A MgO film 21 serving as a protection film is formed on a discharge surface of the dielectric layer 20.
A back glass plate 16 is opposite the front glass plate 18. Address (opposing) electrodes 15 are provided oan the back glass plate 16 so that the address electrodes 15 are orthogonal to the sustain electrodes 19. Barriers 11 are respectively provided between the address electrodes 15. The fluorescent substances 17 each having the red, green and blue light emitting performance are respectively provided between the barriers 11 so that the fluorescent substances 17 cover the respective address electrodes 15. The glass plates 16 and 18 are assembled into a unit so that the tops of the barriers 11 tightly contact the MgO film 21.
FIG. 4 is a waveform diagram of a conventional electrode driving operation on the plasma display panel shown in FIGS. 1 through 3. More particularly, FIG. 4 shows one subfield period in a conventional xe2x80x9caddress period/sustain discharge period separation type write address systemxe2x80x9d.
In the example shown in FIG. 4, one subfield is segmented into a reset period, an address period and a sustain discharge period. During the reset period, all the Y electrodes Y1xe2x88x92YN are reset to 0 V, and simultaneously a whole screen write pulse of a voltage Vs+Vw (approximately equal to 330 V) is applied to the X electrodes. Hence, irrespective of the previous display state, all cells of all display lines are discharged. The potentials of the address electrodes at that time are approximately equal to 100 V (Vaw). Next. the potentials of the X electrodes and the address electrodes are changed to 0 V, a discharge is started in all the cells in such a way that the voltage of the wall charge itself exceeds a discharge starting voltage. In the above discharge, the wall charge is not formed because there is no potential difference between the electrodes. Hence, the space charge is self-neutralized and the discharge is ceased. That is, the self-erase discharge occurs. By the self-erase discharge, all the cells in the panel are changed to an even state having no wall charge. The reset period functions to set all the cells to the even state irrespective of the lighting states of the calls during the previous subfield. Hence, the next address (write) discharge can stably be caused.
In the address period subsequent to the reset period, the address discharge is caused in line-sequential formation in order to turn ON or OFF of the cells in accordance with display data. First, a scan pulse of a xe2x88x92Vy level (approximately equal to xe2x88x92150 V) is serially applied to the Y electrodes, and an address pulse of a voltage Va (approximately equal to 50 V) is selectively applied to address electrodes required to cause the sustain discharge, that is, the address electrodes corresponding to cells to be lighted. Hence, a discharge occurs between the address electrode and the Y electrode of each cell to be lighted. The above discharge functions as a priming, and immediately shifts to a discharge between the X electrode (voltage Vx is equal to 50 V) and the Y electrode. The former discharge will be referred to as priming address discharge, and the later discharge will be referred to as a main address discharge. Hence, a number of wall charges sufficient to realize the sustain discharge is accumulated in the MgO surface 21 on the X and Y electrodes.
The same operation as described above is carried out in each of the other display lines, new display data is written into all the display lines.
During the sustain discharge period subsequent to the address period, a sustain pulse of a voltage Vs (approximately equal to 180 V) is alternatively applied to the Y electrodes and the X electrodes. Hence, image of one subfield can be displayed. In the address period/sustain discharge separation type write address system, the luminescence depends on the length of the sustain discharge period, that is, the number of times that the sustain pulse is repeatedly applied.
FIG. 5 is a timing chart of the address period/sustain discharge separation type write address system, and more particularly exemplarily shows a display method for implementing a 16-gradation display. In the present example, one frame is segmented into four subfield SF1, SF2, SF3 and SF4, which have an identical reset period and an identical address period. The lengths of the sustain discharge in the subfields SF1, SF2, SF3 and SF4 have a ratio of 1:2:4:8. The 16-gradation display can be realized by selecting subfields to be lighted.
The subfields of the above-mentioned driving method have the respective reset periods, in each of the reset periods the whole screen write discharge is caused by applying the whole screen write pulse to the X electrodes. Hence, lighting is carried out during the reset period of each subfield, whereas the reset period does not contribute to image display. The above lighting serves as a factor which degrades the contrast of displayed image.
U.S. patent application Ser. No. 695,061 filed on Aug. 2, 1996 discloses an improved method having a reduced number of times per frame that the whole screen write pulse is repeatedly applied and realizing an improved contrast. The disclosure of the above application is hereby incorporated by reference. In the above method, the whole screen write discharge is caused only in some subfields, and only the erase discharge is caused for the reset periods of the remaining subfields. Hence, it is possible to reduce the number of times that the whole screen write discharge is repeatedly caused and to realize an improved contrast in which lighting which does not contribute to image display is suppressed.
The voltages of various pulses used to correctly light ON cells and not to light OFF cells at all have tolerable ranges. The minimum voltage level of each of the tolerable ranges and the maximum voltage level thereof define a respective drive voltage margin.
A first problem about the drive voltage margin will now be described. In narrow-width pulse erasing in the address electrodes of a simple matrix panel (dual poles), in order to cut an externally applied voltage during the time when a discharge is being formed, most charged particles created at the time of discharging remain in the discharge cell spaces. Then, the charged particles are adhered to the wall charges on the panel dielectric layer due to electrostatic attracting force, and are recombined and erased on the wall surfaces. In the triple-electrode panel having the surface discharge electrodes, the narrow-width pulse erasing operation is caused on the surface discharge electrodes on the identical plate. Hence, the charged particles in the discharge cell spaces are susceptible to the potentials of the address electrodes.
FIG. 6 shows residual wall charges, and more particularly shows that the address electrodes have a voltage Va while the neutralizing discharge using the narrow-width pulse takes place. In this case, a huge number of minus charges is accumulated on the address electrodes, and a failure in erasing thus takes place. FIG. 7 also shows residual wall charges, and more particularly shows the address electrodes are at the ground level GND while the neutralizing discharge using the narrow-width pulse takes place. In this case, a huge number of plus charges is accumulated on the address electrodes, and the erasing thus fails.
In the cases shown in FIGS. 6 and 7, the failure in erasing prevents selective formation of wall charges within the subsequent address period, and thus degrades the drive voltage margin.
A second problem about the drive voltage margin will now be described. In he erasing using the narrow-width pulse within the reset period, if the discharge is started earlier than the expected start timing due to an unevenness of the performance of the pixels and/or variations in the temperature condition, the wall charges may not be erased sufficiently. Additionally, wall charges may be formed which have the polarity opposite to the polarity which the charges have before the erasing. This degrades the drive voltage margin.
A description will now be given of a third problem about the drive voltage margin. FIG. 8 shows an influence by a very weak discharge, and more particularly shows the pulses respectively applied to the address, X and Y electrodes and a discharge light pulse. The discharge light pulses include a very weak light, which is located in the interval between the sustain discharge pulse and the next sustain discharge pulse. The very week discharge does not affect the next sustain discharge itself. Hence, the sustain discharge can certainly take place repeatedly.
However, the inventors found that the very weak discharge greatly affects the erase discharge (which uses the narrow-width pulse in FIG. 8) within the reset period. More paricularly, the very weak discharge decreases the wall charges formed by the sustain discharge, and prevents the normal erase discharge. Hence, the erasing of the wall charges fails. This reduces the drive voltage margin.
A description will now be given of a fourth problem about the drive voltage margin. The fourth problem is serious particularly in the high-contrast driving disclosed in the aforementioned patent. In the proposed high-contrast driving, only the erase discharge is made to take place within the reset period except for some subfields. The inventors found that if an erase pulse is applied so as to erase only cells which are lighted during the immediately previous subfield, the capability of erasing the residual wall charges on the address electrode is degraded as compared to the case where the whole screen with discharge causing the self-erase is employed. As an increased number of subfield has been processed, an increased number of residual wall charges is accumulated on the address electrodes. Hence, the whole screen write discharge for the next frame has an increased load. Hence, the cells do not have an even potential even after the whole screen write discharge is caused. Further, an increased load affects the following address discharges. The above thus decreases the drive voltage margin.
A fifth problem about the drive voltage margin will now be described. FIG. 5 which has been described shows the reset periods, address periods, sustain discharge periods and pause periods. A variation in the total time of the drive periods due to a variation in the number of times that the discharge sustain voltage pulse is repeatedly applied changes the pause periods. Hence, the discharges caused by the voltage pulse applied after the pause periods take place in different manners. Hence, the number of wall charges to be reset is changed, so that the drive voltage margin is degraded.
A sixth problem about the drive voltage margin will be described below. The sixth problem is serious particularly in the high-contrast driving. As has been described, only the erase discharge is caused during the reset period except for some subfields. A single voltage pulse used for the erase discharge cannot reset the charges completely. This leads to a failure in erasing and thus decreases the drive voltage margin.
The erasing of the wall charges using the erase pulse in which the voltage thereof is continuously changed uses a non-linear waveform depending on a resistor and a panel capacitance in order to use a simple circuit configuration. If the discharge takes place in a very slant portion of the waveform of the erase pulse, a failure in erasing takes place.
It is a general object of the present invention to provide a method and device for driving a plasma display in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a method and device for driving a plasma display having an improved drive voltage margin.
The above objects of the present invention are achieved by a method for driving a plasma display panel having first and second plates opposite each other, wherein first and second electrodes are formed on the first plate in parallel and third electrodes are formed on the second plate so as to be orthogonal to the first and second electrodes, and wherein one frame of image includes n subfields (n an integer), and each of the n subfield includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, said method comprising the steps of: applying, within a subfield among the n subfields, a narrow-width pulse having a pulse width equal to or less than 2 xcexcs to the first electrodes in order to cause the erase discharge; and applying a voltage pulse to the third electrodes so that the voltage pulse falls at the same time as the narrow-width pulse falls. Hence, it is possible to solve the above-mentioned first problem and avoid an influence of the potential of the third electrodes at the time of performing the erase discharge using the narrow-width pulse.
The above method may be configured so that: the n subfields include a subfield A during which a whole screen discharge and the erase discharge are both caused, and a subfield B during which the erase discharge is caused without causing the whole screen discharge; and the erase discharge during the reset period of at least the subfield B is caused by the narrow-width pulse. Hence it is possible to solve the first problem and realize a stable operation without creating a large number of wall charges.
The above objects of the present invention are also achieved by a method for driving a plasma display panel wherein one frame of image includes n subfields, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, said method comprising the steps of: applying, within the reset period, a narrow-width pulse having a pulse width equal to or less than 2 xcexcs to the first electrodes in order to cause a first erase discharge; and applying, within the reset period, an erase pulse to the send electrodes in order to cause a second erase discharge, the erase pulse continuously changing a voltage applied to the second electrodes. Hence, it is possible to solve the second problem and to prevent erase wall charges having the inverted polarity.
The above method may be configured so that an interval between the narrow-width pulse and the erase pulse is equal to or greater than 10 xcexcs. Hence, it is possible to reduce a variation in the number of wall charges and thus to more certainly perform the reset operation. Hence, it is possible to stabilize the wall charges which are instable due to the first erase discharge by the narrow-width pulse and more certainly erase the stabilized wall charges by the second erase discharge.
The above objects of the present invention are also achieved by a method for driving a plasma display panel wherein one frame of image includes n subfields, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, said method comprising the step of: repeatedly applying, within a given subfield among the n subfields, the sustain discharge pulse so that a last sustain discharge pulse within the sustain discharge period has a pulse width longer than remaining sustain discharge pulses applied within the sustain discharge period. Hence it is possible to solve the third problem and to cause charged particles created by the sustain discharge pulses to be wall charges. Hence the priming effect due to space charges can be reduced. Thus, it is possible to prevent a very week discharge from occurring after the last sustain discharge pulse within the sustain discharge period.
The above method be configured so that: the n subfields include a subfield A during which a whole screen discharge and the erase discharge are both caused, and a subfield B during which the erase discharge is caused without causing the whole screen discharge; and said given subfield is disposed immediately before the subfield B. It is thus possible to prevent a very weak discharge from occurring after the last sustain discharge pulse within the sustain discharge period.
The above objects of the present invention are also achieved by a method for driving a plasma display panel wherein one frame of image includes n subfields, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, said method comprising the step of: applying, within a given subfield among the n subfields, an erase pulse for causing the erase discharge within the reset period at a first interval from a last sustain discharge pulse in the subfield located immediately before the given subfield, said first interval being equal to a second interval at which sustain discharge pulses repeatedly applied are arranged. It is thus possible to prevent, even if a very weak discharge is caused, the erase discharge from being affected by the very weak discharge.
The above method may be configured so that: the n subfields include a subfield A during which a whole screen discharge and the erase discharge are both caused, and a subfield B during which the erase discharge is causes without causing the whole screen discharge; and said given subfield corresponds to the subfield B. It is thus possible to prevent, even if a very weak discharge is caused in the subfield B, the erase discharge from being affected by the very weak discharge.
The above method may be configured so that an interval between the erase pulse in the subfield B and the last sustain discharge pulse located immediately before said subfield B is equal to or less than 2 xcexcs. Hence it is possible to perform the erase discharge in the next subfield B immediately after the last sustain discharge pulse is applied.
The above objects of the present invention are also achieved by a method for driving a plasma display panel wherein one frame of image includes n subfields, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, said method comprising the step of: applying a voltage pulse to the third electrodes so that the voltage pulse falls at the same time as a last sustain discharge pulse is applied within the sustain discharge period of a subfield located immediately before the reset period of a subfield within which no whole screen write discharge is caused. Hence it is possible to equalize the wall charges on the third electrodes and to more certainly perform the reset operation.
The above objects of the present invention are achieved by a method for driving a plasma display panel wherein one frame of image includes n subfields, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display calls of the panel, an address period for forming wall changes in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, said method comprising the step of: repeatedly applying the sustain discharge pulse within the sustain discharge period at an interval equal to or less than 1 xcexcs. Hence, it is possible to perform the sustain discharge before the space charges due to a very weak discharge are settled to wall discharges. Thus the wall charges on the third electrodes can be reduced and the lead on the erase discharge caused during the reset period can be reduced.
The above objects of the present invention are also achieved by a method for driving a plasma display panel having first and second plates opposite each other, wherein first and second electrodes are formed on the first plate in parallel and third electrodes are formed on the second plate so as to be orthogonal to the first and second electrodes, and wherein one frame of image includes n subfields, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display calls of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, said method comprising the step of: causing, within the reset period of a subfield A among the n subfields, both a whole screen write discharge and the erase discharge so that the erase discharge is caused first aid the whole screen write discharge is caused second. Hence it is possible to solve the fourth problem and to set the residual wall charges to an identical state before the whole screen write discharge. Thus, the load on the whole screen write discharge can be reduced. Hence it is possible to more perfectly erase the charges accumulated an the third electrodes.
The above method may be configured so that it further comprises the step of causing, within the reset period of a subfield B among the n subfields, only the erase discharge without the whole screen discharge. Hence it is possible to solve the fourth problem and to set the residual wall charges to an identical state before the whole screen write discharge. Thus, the load on the whole screen write discharge can be reduced. Hence it is possible to more perfectly erase the charges accumulated on the third electrodes.
The above method may be configured so that it further comprises the step of causing the erase discharge before the whole screen write discharge by repeatedly applying a narrow-width pulse having a pulse width equal to or less than 2 xcexcs to the first electrodes or repeatedly applying an erase pulse continuously changing a voltage applied to the second electrodes or by repeatedly applying both the narrow-width pulse and the erase pulse. Hence it is possible to solve the fourth problem and to set the residual wall charges to an identical state before the whole screen write discharge. Thus, the load on the whole screen write discharge can be reduced. Hence it is possible to more perfectly erase the charges accumulated on the third electrodes.
The above method may be configured so that: the erase discharge is caused within the reset period before the whole screen write discharge is caused; and a voltage of 0 V is applied to the third electrodes when the erase discharge is caused. Thus, the load on the whole screen write discharge can be reduced. Hence it is possible to more perfectly erase the charges accumulated on the third electrodes.
The above method may be configured so that the n subfields include a subfield A during which the whole screen discharge and the erase discharge are both caused during the reset period, and a subfield B during which the erase discharge is caused without causing the whole screen discharge during the reset period. Thus, the load on the whole screen write discharge can be reduced. Hence it is possible to more perfectly erase the charges accumulated on the third electrodes.
The above objects of the present invention are also achieved by a method for driving a plasma display panel having first and second plates opposite each other, wherein first and second electrodes are formed on the first plate in parallel and third electrodes are formed on the second plate so as to be orthogonal to the first and second electrodes, and wherein one frame of image includes n subfields, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, said method comprising the step of: causing, within the reset period of a subfield A among the n subfields, both a whole screen write discharge and the erase discharge by applying a narrow-width pulse equal to or less than 2 xcexcs to the third electrodes to cause the erase discharge after a whole screen write pulse causing the whole screen write discharge falls. Hence it is possible to erase the charges accumulated on the third electrodes more completely and to equalize the wall charges.
The above method may further comprise the step of applying the narrow-width pulse to the third electrodes within 10 xcexcs after the whole screen pulse falls. Hence it is possible to erase the charges accumulated on the third electrodes more completely and to certainly equalize the wall charges.
The above method may further comprise the step of applying, within the reset period, an erase pulse continuously changing a voltage applied to the second electrodes after the whole screen write pulse falls. Hence it is possible to erase the charges accumulated on the third electrodes more completely and to certainly equalize the wall charges.
The above objects of the present invention are achieved by a method for driving a plasma display panel wherein one frame of image includes n subfields weighted, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, the sustain discharge period of each of the n subfields being based on weighting applied thereto, said method comprising the steps of: causing, within the reset period of a subfield A among the n subfields, both a whole screen write discharge and the erase discharge; and causing, within the reset period of a subfield B among the n subfields, the erase discharge without the whole screen write discharge, the reset period within which both the whole screen write discharge and the erase discharge are caused being disposed after a shortest sustain discharge period defined by the weighting. Hence it is possible to solve the fourth problem and to set the residual wall charges to an identical state before the whole screen write discharge. Thus, the load an the whole screen write discharge can be reduced. Hence it is possible to more perfectly erase the charges accumulated on the third electrodes.
The above objects of the present invention are also achieved by a method for driving a plasma display panel wherein one frame of image includes n subfields weighted, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, the sustain discharge period of each of the n subfields being based on weighting applied thereto, said method comprising the steps of: causing, within the reset period of a subfield A among the n subfields, both a whole screen write discharge and the erase discharge; and causing, within the reset period of a subfield B among the n subfields, the erase discharge without the whole screen write discharge, the reset period within which both the whole screen write discharge and the erase discharge are caused being disposed after a longest sustain discharge period defined by the weighting. Hence, the whole screen write discharge is caused when the largest number of charges is accumulated on the third electrodes. Thus it is possible to efficiently perform the whole screen write discharge and to more completely erase the charges accumulated on the third electrodes.
The above objects of the present invention are also achieved by a method for driving a plasma display panel wherein one frame of image includes n subfields weighted and a pause period during which no drive pulses are output, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, the sustain discharge period of each of the n subfields being based on weighting applied thereto, said method comprising the step of: causing, within the reset period of a subfield A among the n subfields, both a whole screen write discharge and the erase discharge, said pause period being a self-erasing period after a whole screen write pulse for causing the whole screen write discharge is caused. Hence it is possible to solve the fifth problem and to reduce a variation in a drive voltage margin dependent on the length of the pause period.
The above method may further comprise the step of causing, within the reset period of a subfield B among the n subfields, the erase discharge without the whole screen write discharge, the pause period being located after the subfield A. Hence it is possible to more effectively reduce a variation in a drive voltage margin dependent on the length of the pause period.
The above objects of the present invention are also achieved by a method for driving a plasma display panel having first and second plates opposite each other, wherein first and second electrodes are formed on the first plate in parallel and third electrodes are formed on the second plate so as to be orthogonal to the first and second electrodes, and wherein one frame of image includes n subfields, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, said method comprising the steps of: applying, within the reset period, a narrow-width pulse having a pulse width equal to or less than 2 xcexcs to the first electrodes; and applying, within the reset period, erase pulses continuously changing a voltage applied to the second electrodes so that a first erase pulse continuously changing the voltage in a positive direction is applied after the narrow-width pulse is applied, and then a second erase pulse continuously changing the voltage in a negative direction or an erase pulse in the negative direction is applied to the second electrodes. Hence it is possible to solve the sixth problem and to more certainly erase the residual wall charges before the address selective discharge and improve the drive voltage margin.
The above method may be configured so that it further comprises the step of applying a third erase pulse continuously changing the voltage in the positive direction. Hence it is possible to more certainly erase the residual wall charges before the address selective discharge and improve the drive voltage margin.
The above method may be configured so that an n+1th erase pulse has a pulse width longer than that of an nth erase pulse. Hence it is possible to solve the sixth problem and to more certainly erase the residual wall charges before the address selective discharge and improve the drive voltage margin.
The above objects of the present invention are also achieved by a method for driving a plasma display panel having first and second plates opposite each other, wherein first and second electrodes are formed on the first plate in parallel and third electrodes are formed on the second plate so as to be orthogonal to the first and second electrodes, and wherein one frame of image includes n subfields, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, said method comprising the steps of: applying, within the reset period, a narrow-width pulse having a pulse width equal to or less than 2 xcexcs to the first electrodes; and applying, within the reset period, erase pulses continuously changing a voltage applied to the second electrodes so that a first erase pulse continuously changing the voltage in a positive direction is applied after the narrow-width pulse is applied, and then a second erase pulse continuously changing the voltage in a position direction is applied to the first electrodes. Hence it is possible to solve the sixth problem and to more certainly erase the residual wall charges before the address selective discharge and improve the drive voltage margin.
It may be preferable that the erase pulses steeply rise. However, in practice, the erase pulses are generated by a resistor and a panel capacitor and rise non-linearly. In this case, it is desired that discharge takes place in a gentle portion of the waveforms of the erase pulses. With the above in mind, there is provided a method for driving a plasma display panel having first and second plates opposite each other, wherein first and second electrodes are formed on the first plate in parallel and third electrodes are formed on the second plate so as to be orthogonal to the first and second electrodes, and wherein one frame of image includes n subfields, and each of the n subfields includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel, said method comprising the step of: consecutively applying, within the reset period, a plurality of reset pulses which erase wall charges and continuously change a voltage applied to any of the first, second and third electrodes in order to cause a discharge at a voltage close to a discharge start voltage. Hence, it is possible to stably and certainly erase (reset) the wall charges in the cells having different discharge start voltages at voltages close to the respective discharge start voltages.
The above method may further comprise the steps of: applying the plurality of reset pulses to the first electrodes; and setting the second voltages to different potentials respectively corresponding to the plurality of reset pulses. Hence, it is possible to stably and certainly erase the wall charges in the cells having different discharge start voltages at voltages close to the respective discharge start voltages.
The above method may further comprise the steps of: applying the plurality of reset pulses to the first electrodes; and setting the third voltages to different potentials respectively corresponding to the plurality of reset pulses. Hence, it is possible to stably and certainly erase (reset) the wall charges in the cells having different discharge start voltages at voltages close to the respective discharge start voltages.
The above method may be configured so that the plurality of reset pulses have an identical voltage slope. Thus, a simple circuit can be used which generates the reset pulses.
The above method may be configured so that a maximum potential difference between the first and second electrodes in response to an n+1th reset pulse among the plurality of reset pulses is greater than that in response to an nth reset pulse among them. Hence, it is possible to reset calls having relatively low discharge start voltages first and to reset cells having relatively high discharge start voltages second.
The method may be configured so that a maximum potential difference between the first and third electrodes in response to an n+1th reset pulse among the plurality of reset pulses is greater than that in response to an nth reset pulse among them. Hence, it is possible to reset cells having relatively low discharge start voltages first and to reset cells having relatively high discharge start voltages second.
The method may be configured so that at least one of the potentials of the second electrodes based on the respective reset pulses is equal to a potential of the second electrodes set during the address period. Hence, a simple circuit can be used which controls the potential of the second electrodes.
The method may he configured so that at least one of the potentials of the third electrodes based on the respective reset pulses is equal to a potential of the third electrodes set during the address period. Hence, a simple circuit can be used which controls the potential of the third electrodes.
The above objects of the present invention are also achieved by a device adapted to a plasma display panel having first and second plates opposite each other, wherein first and second electrodes are formed on the first plate in parallel and third electrodes are formed on the second plate so as to be orthogonal to the first and second electrodes, said device comprising: a first control part which drives the plasma display panel wherein one frame of image includes n subfields, and each of the n subfield includes a reset period for causing an erase discharge to equalize states of wall charges in display cells of the panel, an address period for forming wall charges in the display cells, and a sustain discharge period for causing a sustain discharge based on the wall charges formed during the address period by repeatedly applying a sustain discharge pulse to the panel; a second control part which consecutively applies, within the reset period, a plurality of reset pulses which erase wall charges and continuously change a voltage applied to any of the first, second and third electrodes in order to cause a discharge at a voltage close to a discharge start voltage. Hence, it in possible to stably and certainly erase the wall charges in the cells having different discharge start voltages at voltages close to the respective discharge start voltages.